Job Description

Application Window: Expected to close 12/20/24. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed. Your Impact As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, power, and area specifications. This role involves coordinating cross-functional teams, guiding design methodologies, and addressing technical challenges throughout the development process to ensure successful tape-out and compliance with industry standards. Responsibilities include: Lead chip-level PNR activities, from floor planning, bump and RDL planning, power grid design to clock planning, routing, and timing closure. Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results. Work closely with block and TOP level physical implementation, IP development teams to resolve PV issues and address to proper owners. Deploy and improve physical verification flows and methodologies. Develop custom checks as per need for verification robustness. Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend, integration, and verification teams. Minimum Qualifications: BS/MS in Electrical Engineering or Computer Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification. Experience in deep submicron CMOS technologies. Experience with physical verification (DRC, LVS, ERC, ANT), debug, and solution. Scripting experience in TCL, Perl, or Makefile to streamline and automate workflows. Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion Compiler. Preferred Qualifications: Extensive experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support. Experience on 5nm nodes and below. Experience working with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams. Experience working with Package and floorplan teams to define padring and bump-map design. Why Cisco? #WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. Nearly every internet connection around the world touches Cisco. We're the Internet's optimists. Our technology makes sure the data travelling at light speed across connections does so securely. We tackle whatever challenges come our way. We have each other's backs, we recognize our accomplishments, and we grow together. We celebrate and support one another - from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that). We know that powering an inclusive future starts with us. Because without diversity and a dedication to equality, there is no moving forward. Our 30 Inclusive Communities, that bring people together around commonalities or passions, are leading the way. So, you have colorful hair? Don't care. Tattoos? Show off your ink. Like polka dots? That's cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! #WeAreCisco #J-18808-Ljbffr Cisco Systems, Inc.

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