Job Description

Circuits Physical Design Engineer Santa Clara,California,United States Hardware Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on silicon validation, making a critical impact delivering products to market quickly. **Description** Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure & signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation. **Minimum Qualifications** + BS and a minimum of 3 years of relevant industry experience.

• *Key Qualifications**
• *Preferred Qualifications**

• We are looking for applicants with at least 3 years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Familiar with development of block/partitions for silicon validation of foundation Ips.
• Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is a strong plus.
• Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is a strong plus.
• Hands-on experience with ECO implementation, both functional and timing closure is a strong plus.
• Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
• Strong scripting skills using Perl/Tcl.
• Strong written/verbal communication skills.

• *Education & Experience**
• *Additional Requirements**
• *Pay & Benefits**

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $136,300 and $248,700, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.Learn more ( ) about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. ( \_EEOC\_KnowYourRights6.12ScreenRdr.pdf)

**Apple Footer** Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) . Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) . Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines (opens in a new window) applicable in your area. Apple participates in the E-Verify program in certain locations as required by law. Learn more about the E-Verify program (Opens in a new window) . Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) . Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) . #J-18808-Ljbffr Apple

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